URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] [rtl/] [verilog/] - Rev 261

Rev	Log message	Author	Age	Path
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7866d 20h	/ethmac/tags/rel_20/rtl/verilog/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7870d 20h	/ethmac/tags/rel_20/rtl/verilog/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7873d 20h	/ethmac/tags/rel_20/rtl/verilog/
218	Typo error fixed. (When using Bist)	mohor	7873d 22h	/ethmac/tags/rel_20/rtl/verilog/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7874d 19h	/ethmac/tags/rel_20/rtl/verilog/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7874d 19h	/ethmac/tags/rel_20/rtl/verilog/
212	Minor $display change.	mohor	7874d 19h	/ethmac/tags/rel_20/rtl/verilog/
211	Bist added.	mohor	7874d 19h	/ethmac/tags/rel_20/rtl/verilog/
210	BIST added.	mohor	7874d 19h	/ethmac/tags/rel_20/rtl/verilog/
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7891d 18h	/ethmac/tags/rel_20/rtl/verilog/