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[/] [ethmac/] [tags/] [rel_20/] [rtl/] [verilog/] - Rev 269

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Rev	Log message	Author	Age	Path
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7779d 08h	/ethmac/tags/rel_20/rtl/verilog
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	7838d 07h	/ethmac/tags/rel_20/rtl/verilog
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7838d 18h	/ethmac/tags/rel_20/rtl/verilog
259	In loopback rx_clk is not looped back. Possible CRC error. Consider if usage of additional logic is necessery (FIFO for looping the data).	mohor	7839d 20h	/ethmac/tags/rel_20/rtl/verilog
257	When TxUsedData and CtrlMux occur at the same time, byte counter needs to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.	mohor	7839d 20h	/ethmac/tags/rel_20/rtl/verilog
256	TxDone and TxAbort changed so they're not propagated to the wishbone module when control frame is transmitted.	mohor	7839d 20h	/ethmac/tags/rel_20/rtl/verilog
255	TPauseRq synchronized to tx_clk.	mohor	7839d 20h	/ethmac/tags/rel_20/rtl/verilog
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	7841d 02h	/ethmac/tags/rel_20/rtl/verilog
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	7841d 03h	/ethmac/tags/rel_20/rtl/verilog
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7841d 03h	/ethmac/tags/rel_20/rtl/verilog
248	wb_rst_i is used for MIIM reset.	mohor	7842d 03h	/ethmac/tags/rel_20/rtl/verilog
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7845d 06h	/ethmac/tags/rel_20/rtl/verilog
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7846d 02h	/ethmac/tags/rel_20/rtl/verilog
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7846d 22h	/ethmac/tags/rel_20/rtl/verilog
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7846d 22h	/ethmac/tags/rel_20/rtl/verilog
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7846d 22h	/ethmac/tags/rel_20/rtl/verilog
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7846d 22h	/ethmac/tags/rel_20/rtl/verilog
238	Defines fixed to use generic RAM by default.	mohor	7859d 02h	/ethmac/tags/rel_20/rtl/verilog
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7861d 07h	/ethmac/tags/rel_20/rtl/verilog
232	fpga define added.	mohor	7867d 01h	/ethmac/tags/rel_20/rtl/verilog
229	case changed to casex.	mohor	7872d 23h	/ethmac/tags/rel_20/rtl/verilog
227	Changed BIST scan signals.	tadejm	7873d 03h	/ethmac/tags/rel_20/rtl/verilog
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7873d 04h	/ethmac/tags/rel_20/rtl/verilog
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7877d 04h	/ethmac/tags/rel_20/rtl/verilog
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7880d 05h	/ethmac/tags/rel_20/rtl/verilog
218	Typo error fixed. (When using Bist)	mohor	7880d 07h	/ethmac/tags/rel_20/rtl/verilog
214	Signals for WISHBONE B3 compliant interface added.	mohor	7881d 03h	/ethmac/tags/rel_20/rtl/verilog
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7881d 03h	/ethmac/tags/rel_20/rtl/verilog
212	Minor $display change.	mohor	7881d 03h	/ethmac/tags/rel_20/rtl/verilog
211	Bist added.	mohor	7881d 04h	/ethmac/tags/rel_20/rtl/verilog

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[/] [ethmac/] [tags/] [rel_20/] [rtl/] [verilog/] - Rev 269

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