OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] [rtl/] [verilog/] - Rev 275

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
275 Fix MTxErr or prevent sending too big frames. mohor 7765d 22h /ethmac/tags/rel_20/rtl/verilog/
272 When control packets were received, they were ignored in some cases. tadejm 7766d 17h /ethmac/tags/rel_20/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7767d 19h /ethmac/tags/rel_20/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7768d 19h /ethmac/tags/rel_20/rtl/verilog/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7827d 18h /ethmac/tags/rel_20/rtl/verilog/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7828d 05h /ethmac/tags/rel_20/rtl/verilog/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7829d 07h /ethmac/tags/rel_20/rtl/verilog/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7829d 07h /ethmac/tags/rel_20/rtl/verilog/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7829d 07h /ethmac/tags/rel_20/rtl/verilog/
255 TPauseRq synchronized to tx_clk. mohor 7829d 07h /ethmac/tags/rel_20/rtl/verilog/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7830d 13h /ethmac/tags/rel_20/rtl/verilog/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7830d 14h /ethmac/tags/rel_20/rtl/verilog/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7830d 14h /ethmac/tags/rel_20/rtl/verilog/
248 wb_rst_i is used for MIIM reset. mohor 7831d 14h /ethmac/tags/rel_20/rtl/verilog/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7834d 17h /ethmac/tags/rel_20/rtl/verilog/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7835d 13h /ethmac/tags/rel_20/rtl/verilog/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7836d 09h /ethmac/tags/rel_20/rtl/verilog/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7836d 09h /ethmac/tags/rel_20/rtl/verilog/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7836d 09h /ethmac/tags/rel_20/rtl/verilog/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7836d 09h /ethmac/tags/rel_20/rtl/verilog/
238 Defines fixed to use generic RAM by default. mohor 7848d 13h /ethmac/tags/rel_20/rtl/verilog/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7850d 18h /ethmac/tags/rel_20/rtl/verilog/
232 fpga define added. mohor 7856d 12h /ethmac/tags/rel_20/rtl/verilog/
229 case changed to casex. mohor 7862d 10h /ethmac/tags/rel_20/rtl/verilog/
227 Changed BIST scan signals. tadejm 7862d 14h /ethmac/tags/rel_20/rtl/verilog/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7862d 15h /ethmac/tags/rel_20/rtl/verilog/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7866d 15h /ethmac/tags/rel_20/rtl/verilog/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7869d 16h /ethmac/tags/rel_20/rtl/verilog/
218 Typo error fixed. (When using Bist) mohor 7869d 18h /ethmac/tags/rel_20/rtl/verilog/
214 Signals for WISHBONE B3 compliant interface added. mohor 7870d 14h /ethmac/tags/rel_20/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.