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[/] [ethmac/] [tags/] [rel_20/] [rtl/] [verilog/] - Rev 297


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Rev Log message Author Age Path
297 Artisan ram instance added. simons 6202d 23h /ethmac/tags/rel_20/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 6239d 00h /ethmac/tags/rel_20/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 6265d 03h /ethmac/tags/rel_20/rtl/verilog/
285 Binary operator used instead of unary (xnor). mohor 6265d 04h /ethmac/tags/rel_20/rtl/verilog/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 6293d 05h /ethmac/tags/rel_20/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 6320d 23h /ethmac/tags/rel_20/rtl/verilog/
280 Reset has priority in some flipflops. mohor 6399d 00h /ethmac/tags/rel_20/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 6399d 02h /ethmac/tags/rel_20/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 6399d 02h /ethmac/tags/rel_20/rtl/verilog/
276 Defer indication changed. tadejm 6399d 02h /ethmac/tags/rel_20/rtl/verilog/
275 Fix MTxErr or prevent sending too big frames. mohor 6406d 06h /ethmac/tags/rel_20/rtl/verilog/
272 When control packets were received, they were ignored in some cases. tadejm 6407d 01h /ethmac/tags/rel_20/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6408d 03h /ethmac/tags/rel_20/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 6409d 03h /ethmac/tags/rel_20/rtl/verilog/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 6468d 02h /ethmac/tags/rel_20/rtl/verilog/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
mohor 6468d 13h /ethmac/tags/rel_20/rtl/verilog/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 6469d 15h /ethmac/tags/rel_20/rtl/verilog/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 6469d 15h /ethmac/tags/rel_20/rtl/verilog/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 6469d 15h /ethmac/tags/rel_20/rtl/verilog/
255 TPauseRq synchronized to tx_clk. mohor 6469d 15h /ethmac/tags/rel_20/rtl/verilog/

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