OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] [rtl/] [verilog/] - Rev 338

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 5478d 14h /ethmac/tags/rel_20/rtl/verilog
335 New directory structure. root 5535d 19h /ethmac/tags/rel_20/rtl/verilog
298 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7569d 12h /ethmac/tags/rel_20/rtl/verilog
297 Artisan ram instance added. simons 7569d 12h /ethmac/tags/rel_20/rtl/verilog
288 This file was not part of the RTL before, but it should be here. simons 7605d 14h /ethmac/tags/rel_20/rtl/verilog
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7631d 17h /ethmac/tags/rel_20/rtl/verilog
285 Binary operator used instead of unary (xnor). mohor 7631d 18h /ethmac/tags/rel_20/rtl/verilog
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7659d 19h /ethmac/tags/rel_20/rtl/verilog
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7687d 13h /ethmac/tags/rel_20/rtl/verilog
280 Reset has priority in some flipflops. mohor 7765d 14h /ethmac/tags/rel_20/rtl/verilog
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7765d 15h /ethmac/tags/rel_20/rtl/verilog
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7765d 15h /ethmac/tags/rel_20/rtl/verilog
276 Defer indication changed. tadejm 7765d 16h /ethmac/tags/rel_20/rtl/verilog
275 Fix MTxErr or prevent sending too big frames. mohor 7772d 20h /ethmac/tags/rel_20/rtl/verilog
272 When control packets were received, they were ignored in some cases. tadejm 7773d 15h /ethmac/tags/rel_20/rtl/verilog
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7774d 17h /ethmac/tags/rel_20/rtl/verilog
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7775d 17h /ethmac/tags/rel_20/rtl/verilog
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7834d 16h /ethmac/tags/rel_20/rtl/verilog
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7835d 03h /ethmac/tags/rel_20/rtl/verilog
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7836d 04h /ethmac/tags/rel_20/rtl/verilog
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7836d 05h /ethmac/tags/rel_20/rtl/verilog
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7836d 05h /ethmac/tags/rel_20/rtl/verilog
255 TPauseRq synchronized to tx_clk. mohor 7836d 05h /ethmac/tags/rel_20/rtl/verilog
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7837d 11h /ethmac/tags/rel_20/rtl/verilog
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7837d 11h /ethmac/tags/rel_20/rtl/verilog
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7837d 11h /ethmac/tags/rel_20/rtl/verilog
248 wb_rst_i is used for MIIM reset. mohor 7838d 11h /ethmac/tags/rel_20/rtl/verilog
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7841d 15h /ethmac/tags/rel_20/rtl/verilog
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7842d 10h /ethmac/tags/rel_20/rtl/verilog
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7843d 07h /ethmac/tags/rel_20/rtl/verilog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.