URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] [rtl/] [verilog/] - Rev 338

Rev	Log message	Author	Age	Path
257	When TxUsedData and CtrlMux occur at the same time, byte counter needs to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.	mohor	7836d 02h	/ethmac/tags/rel_20/rtl/verilog
256	TxDone and TxAbort changed so they're not propagated to the wishbone module when control frame is transmitted.	mohor	7836d 02h	/ethmac/tags/rel_20/rtl/verilog
255	TPauseRq synchronized to tx_clk.	mohor	7836d 02h	/ethmac/tags/rel_20/rtl/verilog
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	7837d 08h	/ethmac/tags/rel_20/rtl/verilog
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	7837d 09h	/ethmac/tags/rel_20/rtl/verilog
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7837d 09h	/ethmac/tags/rel_20/rtl/verilog
248	wb_rst_i is used for MIIM reset.	mohor	7838d 09h	/ethmac/tags/rel_20/rtl/verilog
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7841d 12h	/ethmac/tags/rel_20/rtl/verilog
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7842d 08h	/ethmac/tags/rel_20/rtl/verilog
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7843d 04h	/ethmac/tags/rel_20/rtl/verilog