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Rev Log message Author Age Path
180 Bench outputs data to display every 128 bytes. mohor 7832d 12h /ethmac/tags/rel_21/
179 Beautiful tests merget together mohor 7832d 13h /ethmac/tags/rel_21/
178 Rearanged testcases mohor 7832d 13h /ethmac/tags/rel_21/
177 Bug in MIIM fixed. mohor 7832d 17h /ethmac/tags/rel_21/
176 lists changed to new directory structure mohor 7832d 18h /ethmac/tags/rel_21/
175 Script fixed to new dir structure mohor 7832d 18h /ethmac/tags/rel_21/
174 Directory keeper mohor 7832d 19h /ethmac/tags/rel_21/
173 Keeps the directory mohor 7832d 19h /ethmac/tags/rel_21/
172 NCSIM simulation environment added to cvs mohor 7832d 19h /ethmac/tags/rel_21/
171 NCSIM simulation environment added. mohor 7832d 19h /ethmac/tags/rel_21/
170 Headers changed. mohor 7832d 19h /ethmac/tags/rel_21/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7832d 20h /ethmac/tags/rel_21/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7833d 17h /ethmac/tags/rel_21/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7834d 17h /ethmac/tags/rel_21/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7835d 18h /ethmac/tags/rel_21/
165 HASH improvement needed. mohor 7835d 21h /ethmac/tags/rel_21/
164 Ethernet debug registers removed. mohor 7835d 21h /ethmac/tags/rel_21/
163 Another temporary version. Core is almost finished. Testbench not included,
yet"
mohor 7836d 13h /ethmac/tags/rel_21/
162 Another temporary version. Core is almost finished. Testbench not included,
yet.
mohor 7836d 13h /ethmac/tags/rel_21/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7836d 19h /ethmac/tags/rel_21/

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