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162 Another temporary version. Core is almost finished. Testbench not included,
yet.
mohor 8193d 22h /ethmac/tags/rel_21/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 8194d 04h /ethmac/tags/rel_21/
160 error acknowledge cycle termination added to display. mohor 8194d 04h /ethmac/tags/rel_21/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 8195d 00h /ethmac/tags/rel_21/
158 Typo fixed. mohor 8195d 00h /ethmac/tags/rel_21/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 8197d 06h /ethmac/tags/rel_21/
156 Valid testbench. mohor 8197d 06h /ethmac/tags/rel_21/
155 Minor changes. mohor 8197d 06h /ethmac/tags/rel_21/
154 Design document is still under construction. mohor 8198d 05h /ethmac/tags/rel_21/
153 Temp version (backup). mohor 8198d 20h /ethmac/tags/rel_21/

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