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[/] [ethmac/] [tags/] [rel_21/] - Rev 221

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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7873d 06h /ethmac/tags/rel_21
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7876d 06h /ethmac/tags/rel_21
218 Typo error fixed. (When using Bist) mohor 7876d 08h /ethmac/tags/rel_21
217 Bist supported. mohor 7876d 08h /ethmac/tags/rel_21
216 Bist signals added. mohor 7876d 08h /ethmac/tags/rel_21
215 Bist supported. mohor 7876d 09h /ethmac/tags/rel_21
214 Signals for WISHBONE B3 compliant interface added. mohor 7877d 05h /ethmac/tags/rel_21
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7877d 05h /ethmac/tags/rel_21
212 Minor $display change. mohor 7877d 05h /ethmac/tags/rel_21
211 Bist added. mohor 7877d 05h /ethmac/tags/rel_21
210 BIST added. mohor 7877d 05h /ethmac/tags/rel_21
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7878d 08h /ethmac/tags/rel_21
208 Virtual Silicon RAMs moved to lib directory tadej 7894d 02h /ethmac/tags/rel_21
207 Virtual Silicon RAM support fixed tadej 7894d 03h /ethmac/tags/rel_21
206 Virtual Silicon RAM added to the simulation. mohor 7894d 03h /ethmac/tags/rel_21
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7894d 03h /ethmac/tags/rel_21
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7894d 03h /ethmac/tags/rel_21
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7894d 03h /ethmac/tags/rel_21
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7897d 05h /ethmac/tags/rel_21
201 Core size added to the document. mohor 7897d 05h /ethmac/tags/rel_21

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