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[/] [ethmac/] [tags/] [rel_21/] - Rev 239

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Rev Log message Author Age Path
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7844d 06h /ethmac/tags/rel_21
238 Defines fixed to use generic RAM by default. mohor 7856d 10h /ethmac/tags/rel_21
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7858d 15h /ethmac/tags/rel_21
235 rev 4. mohor 7859d 06h /ethmac/tags/rel_21
234 Figure list assed to the revision 3. mohor 7859d 14h /ethmac/tags/rel_21
233 Revision 0.3 released. Some figures added. mohor 7859d 14h /ethmac/tags/rel_21
232 fpga define added. mohor 7864d 09h /ethmac/tags/rel_21
231 Description of Core Modules added (figure). mohor 7866d 11h /ethmac/tags/rel_21
229 case changed to casex. mohor 7870d 07h /ethmac/tags/rel_21
227 Changed BIST scan signals. tadejm 7870d 11h /ethmac/tags/rel_21
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7870d 12h /ethmac/tags/rel_21
225 Some minor changes. tadejm 7870d 13h /ethmac/tags/rel_21
224 Signals for a wave window in Modelsim. tadejm 7870d 14h /ethmac/tags/rel_21
223 Some code changed due to bug fixes. tadejm 7870d 14h /ethmac/tags/rel_21
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7874d 12h /ethmac/tags/rel_21
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7877d 13h /ethmac/tags/rel_21
218 Typo error fixed. (When using Bist) mohor 7877d 14h /ethmac/tags/rel_21
217 Bist supported. mohor 7877d 15h /ethmac/tags/rel_21
216 Bist signals added. mohor 7877d 15h /ethmac/tags/rel_21
215 Bist supported. mohor 7877d 15h /ethmac/tags/rel_21
214 Signals for WISHBONE B3 compliant interface added. mohor 7878d 11h /ethmac/tags/rel_21
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7878d 11h /ethmac/tags/rel_21
212 Minor $display change. mohor 7878d 11h /ethmac/tags/rel_21
211 Bist added. mohor 7878d 12h /ethmac/tags/rel_21
210 BIST added. mohor 7878d 12h /ethmac/tags/rel_21
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7879d 15h /ethmac/tags/rel_21
208 Virtual Silicon RAMs moved to lib directory tadej 7895d 09h /ethmac/tags/rel_21
207 Virtual Silicon RAM support fixed tadej 7895d 09h /ethmac/tags/rel_21
206 Virtual Silicon RAM added to the simulation. mohor 7895d 09h /ethmac/tags/rel_21
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7895d 10h /ethmac/tags/rel_21

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