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252 Just some updates. tadejm 7828d 07h /ethmac/tags/rel_21
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7828d 07h /ethmac/tags/rel_21
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7828d 07h /ethmac/tags/rel_21
248 wb_rst_i is used for MIIM reset. mohor 7829d 07h /ethmac/tags/rel_21
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7832d 11h /ethmac/tags/rel_21
245 Rev 1.7. mohor 7833d 04h /ethmac/tags/rel_21
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7833d 06h /ethmac/tags/rel_21
243 Late collision is not reported any more. tadejm 7833d 12h /ethmac/tags/rel_21
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7834d 02h /ethmac/tags/rel_21
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7834d 03h /ethmac/tags/rel_21
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7834d 03h /ethmac/tags/rel_21
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7834d 03h /ethmac/tags/rel_21
238 Defines fixed to use generic RAM by default. mohor 7846d 07h /ethmac/tags/rel_21
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7848d 12h /ethmac/tags/rel_21
235 rev 4. mohor 7849d 03h /ethmac/tags/rel_21
234 Figure list assed to the revision 3. mohor 7849d 11h /ethmac/tags/rel_21
233 Revision 0.3 released. Some figures added. mohor 7849d 11h /ethmac/tags/rel_21
232 fpga define added. mohor 7854d 06h /ethmac/tags/rel_21
231 Description of Core Modules added (figure). mohor 7856d 07h /ethmac/tags/rel_21
229 case changed to casex. mohor 7860d 04h /ethmac/tags/rel_21
227 Changed BIST scan signals. tadejm 7860d 08h /ethmac/tags/rel_21
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7860d 09h /ethmac/tags/rel_21
225 Some minor changes. tadejm 7860d 09h /ethmac/tags/rel_21
224 Signals for a wave window in Modelsim. tadejm 7860d 11h /ethmac/tags/rel_21
223 Some code changed due to bug fixes. tadejm 7860d 11h /ethmac/tags/rel_21
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7864d 09h /ethmac/tags/rel_21
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7867d 09h /ethmac/tags/rel_21
218 Typo error fixed. (When using Bist) mohor 7867d 11h /ethmac/tags/rel_21
217 Bist supported. mohor 7867d 11h /ethmac/tags/rel_21
216 Bist signals added. mohor 7867d 12h /ethmac/tags/rel_21

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