OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_21/] [rtl/] - Rev 240

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6555d 14h /ethmac/tags/rel_21/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6555d 14h /ethmac/tags/rel_21/rtl/
238 Defines fixed to use generic RAM by default. mohor 6567d 18h /ethmac/tags/rel_21/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6570d 00h /ethmac/tags/rel_21/rtl/
232 fpga define added. mohor 6575d 18h /ethmac/tags/rel_21/rtl/
229 case changed to casex. mohor 6581d 16h /ethmac/tags/rel_21/rtl/
227 Changed BIST scan signals. tadejm 6581d 20h /ethmac/tags/rel_21/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6581d 21h /ethmac/tags/rel_21/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6585d 21h /ethmac/tags/rel_21/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6588d 21h /ethmac/tags/rel_21/rtl/
218 Typo error fixed. (When using Bist) mohor 6588d 23h /ethmac/tags/rel_21/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 6589d 20h /ethmac/tags/rel_21/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6589d 20h /ethmac/tags/rel_21/rtl/
212 Minor $display change. mohor 6589d 20h /ethmac/tags/rel_21/rtl/
211 Bist added. mohor 6589d 20h /ethmac/tags/rel_21/rtl/
210 BIST added. mohor 6589d 20h /ethmac/tags/rel_21/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6606d 18h /ethmac/tags/rel_21/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6606d 18h /ethmac/tags/rel_21/rtl/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6609d 19h /ethmac/tags/rel_21/rtl/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 6617d 22h /ethmac/tags/rel_21/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.