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Rev Log message Author Age Path
245 Rev 1.7. mohor 7854d 11h /ethmac/tags/rel_21
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7854d 13h /ethmac/tags/rel_21
243 Late collision is not reported any more. tadejm 7854d 19h /ethmac/tags/rel_21
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7855d 09h /ethmac/tags/rel_21
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7855d 09h /ethmac/tags/rel_21
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7855d 10h /ethmac/tags/rel_21
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7855d 10h /ethmac/tags/rel_21
238 Defines fixed to use generic RAM by default. mohor 7867d 14h /ethmac/tags/rel_21
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7869d 19h /ethmac/tags/rel_21
235 rev 4. mohor 7870d 10h /ethmac/tags/rel_21
234 Figure list assed to the revision 3. mohor 7870d 18h /ethmac/tags/rel_21
233 Revision 0.3 released. Some figures added. mohor 7870d 18h /ethmac/tags/rel_21
232 fpga define added. mohor 7875d 13h /ethmac/tags/rel_21
231 Description of Core Modules added (figure). mohor 7877d 14h /ethmac/tags/rel_21
229 case changed to casex. mohor 7881d 11h /ethmac/tags/rel_21
227 Changed BIST scan signals. tadejm 7881d 15h /ethmac/tags/rel_21
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7881d 16h /ethmac/tags/rel_21
225 Some minor changes. tadejm 7881d 16h /ethmac/tags/rel_21
224 Signals for a wave window in Modelsim. tadejm 7881d 18h /ethmac/tags/rel_21
223 Some code changed due to bug fixes. tadejm 7881d 18h /ethmac/tags/rel_21
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7885d 16h /ethmac/tags/rel_21
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7888d 16h /ethmac/tags/rel_21
218 Typo error fixed. (When using Bist) mohor 7888d 18h /ethmac/tags/rel_21
217 Bist supported. mohor 7888d 18h /ethmac/tags/rel_21
216 Bist signals added. mohor 7888d 18h /ethmac/tags/rel_21
215 Bist supported. mohor 7888d 19h /ethmac/tags/rel_21
214 Signals for WISHBONE B3 compliant interface added. mohor 7889d 15h /ethmac/tags/rel_21
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7889d 15h /ethmac/tags/rel_21
212 Minor $display change. mohor 7889d 15h /ethmac/tags/rel_21
211 Bist added. mohor 7889d 15h /ethmac/tags/rel_21

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