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[/] [ethmac/] [tags/] [rel_21] - Rev 263

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263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7258d 09h /ethmac/tags/rel_21
262 Version 1.18 released.
MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER
register. Control Frame bit (CF) added to the RX buffer descriptor. Control
frame detection section updated.
mohor 7258d 09h /ethmac/tags/rel_21
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7258d 09h /ethmac/tags/rel_21
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7258d 21h /ethmac/tags/rel_21
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 7259d 10h /ethmac/tags/rel_21
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 7259d 11h /ethmac/tags/rel_21
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 7259d 11h /ethmac/tags/rel_21
255 TPauseRq synchronized to tx_clk. mohor 7259d 11h /ethmac/tags/rel_21
254 Temp version. mohor 7260d 14h /ethmac/tags/rel_21
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7260d 17h /ethmac/tags/rel_21
252 Just some updates. tadejm 7260d 17h /ethmac/tags/rel_21
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7260d 17h /ethmac/tags/rel_21
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7260d 17h /ethmac/tags/rel_21
248 wb_rst_i is used for MIIM reset. mohor 7261d 17h /ethmac/tags/rel_21
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7264d 20h /ethmac/tags/rel_21
245 Rev 1.7. mohor 7265d 14h /ethmac/tags/rel_21
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7265d 16h /ethmac/tags/rel_21
243 Late collision is not reported any more. tadejm 7265d 22h /ethmac/tags/rel_21
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7266d 12h /ethmac/tags/rel_21
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7266d 12h /ethmac/tags/rel_21

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