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29 Generic memory model is used. Defines are changed for the same reason. mohor 8223d 00h /ethmac/tags/rel_22/
28 New release. Name changed to lower case. mohor 8225d 16h /ethmac/tags/rel_22/
27 File names changed to lower case. mohor 8225d 16h /ethmac/tags/rel_22/
26 First release of product brief. mohor 8225d 16h /ethmac/tags/rel_22/
25 First release of product brief. mohor 8225d 16h /ethmac/tags/rel_22/
24 Log file added. mohor 8248d 03h /ethmac/tags/rel_22/
23 Number of addresses (wb_adr_i) minimized. mohor 8248d 03h /ethmac/tags/rel_22/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8248d 06h /ethmac/tags/rel_22/
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 8249d 03h /ethmac/tags/rel_22/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8273d 00h /ethmac/tags/rel_22/

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