OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_23/] - Rev 240

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7836d 18h /ethmac/tags/rel_23/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7836d 18h /ethmac/tags/rel_23/
238 Defines fixed to use generic RAM by default. mohor 7848d 22h /ethmac/tags/rel_23/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7851d 03h /ethmac/tags/rel_23/
235 rev 4. mohor 7851d 18h /ethmac/tags/rel_23/
234 Figure list assed to the revision 3. mohor 7852d 02h /ethmac/tags/rel_23/
233 Revision 0.3 released. Some figures added. mohor 7852d 02h /ethmac/tags/rel_23/
232 fpga define added. mohor 7856d 21h /ethmac/tags/rel_23/
231 Description of Core Modules added (figure). mohor 7858d 22h /ethmac/tags/rel_23/
229 case changed to casex. mohor 7862d 19h /ethmac/tags/rel_23/
227 Changed BIST scan signals. tadejm 7862d 23h /ethmac/tags/rel_23/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7863d 00h /ethmac/tags/rel_23/
225 Some minor changes. tadejm 7863d 00h /ethmac/tags/rel_23/
224 Signals for a wave window in Modelsim. tadejm 7863d 02h /ethmac/tags/rel_23/
223 Some code changed due to bug fixes. tadejm 7863d 02h /ethmac/tags/rel_23/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7867d 00h /ethmac/tags/rel_23/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7870d 00h /ethmac/tags/rel_23/
218 Typo error fixed. (When using Bist) mohor 7870d 02h /ethmac/tags/rel_23/
217 Bist supported. mohor 7870d 02h /ethmac/tags/rel_23/
216 Bist signals added. mohor 7870d 02h /ethmac/tags/rel_23/
215 Bist supported. mohor 7870d 03h /ethmac/tags/rel_23/
214 Signals for WISHBONE B3 compliant interface added. mohor 7870d 23h /ethmac/tags/rel_23/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7870d 23h /ethmac/tags/rel_23/
212 Minor $display change. mohor 7870d 23h /ethmac/tags/rel_23/
211 Bist added. mohor 7870d 23h /ethmac/tags/rel_23/
210 BIST added. mohor 7870d 23h /ethmac/tags/rel_23/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7872d 03h /ethmac/tags/rel_23/
208 Virtual Silicon RAMs moved to lib directory tadej 7887d 21h /ethmac/tags/rel_23/
207 Virtual Silicon RAM support fixed tadej 7887d 21h /ethmac/tags/rel_23/
206 Virtual Silicon RAM added to the simulation. mohor 7887d 21h /ethmac/tags/rel_23/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.