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35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8187d 08h /ethmac/tags/rel_23/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8187d 08h /ethmac/tags/rel_23/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8187d 12h /ethmac/tags/rel_23/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8187d 13h /ethmac/tags/rel_23/
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8187d 13h /ethmac/tags/rel_23/
30 BD section updated. mohor 8189d 10h /ethmac/tags/rel_23/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8209d 09h /ethmac/tags/rel_23/
28 New release. Name changed to lower case. mohor 8212d 00h /ethmac/tags/rel_23/
27 File names changed to lower case. mohor 8212d 00h /ethmac/tags/rel_23/
26 First release of product brief. mohor 8212d 00h /ethmac/tags/rel_23/
25 First release of product brief. mohor 8212d 00h /ethmac/tags/rel_23/
24 Log file added. mohor 8234d 11h /ethmac/tags/rel_23/
23 Number of addresses (wb_adr_i) minimized. mohor 8234d 12h /ethmac/tags/rel_23/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8234d 14h /ethmac/tags/rel_23/
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8235d 11h /ethmac/tags/rel_23/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8259d 08h /ethmac/tags/rel_23/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8259d 08h /ethmac/tags/rel_23/
18 Few little NCSIM warnings fixed. mohor 8272d 09h /ethmac/tags/rel_23/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8299d 09h /ethmac/tags/rel_23/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8306d 15h /ethmac/tags/rel_23/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8308d 08h /ethmac/tags/rel_23/
14 Unconnected signals are now connected. mohor 8312d 14h /ethmac/tags/rel_23/
13 New directory structure. Files upodated and put together. mohor 8314d 22h /ethmac/tags/rel_23/
12 Directory structure changed. Files checked and joind together. mohor 8315d 01h /ethmac/tags/rel_23/
11 Directory structure changed. Files checked and joind together. mohor 8315d 02h /ethmac/tags/rel_23/
10 Directory structure changed. Files checked and joind together. mohor 8315d 02h /ethmac/tags/rel_23/
9 Documentation updated to be synchronized to the verilog files. mohor 8342d 10h /ethmac/tags/rel_23/
8 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.		 mohor 8369d 15h /ethmac/tags/rel_23/
7 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.		 mohor 8369d 15h /ethmac/tags/rel_23/
6 no message mohor 8369d 15h /ethmac/tags/rel_23/

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