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[/] [ethmac/] [tags/] [rel_23/] [rtl/] [verilog/] - Rev 301

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Rev Log message Author Age Path
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7532d 20h /ethmac/tags/rel_23/rtl/verilog/
297 Artisan ram instance added. simons 7585d 19h /ethmac/tags/rel_23/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 7621d 21h /ethmac/tags/rel_23/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7648d 00h /ethmac/tags/rel_23/rtl/verilog/
285 Binary operator used instead of unary (xnor). mohor 7648d 00h /ethmac/tags/rel_23/rtl/verilog/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7676d 02h /ethmac/tags/rel_23/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7703d 19h /ethmac/tags/rel_23/rtl/verilog/
280 Reset has priority in some flipflops. mohor 7781d 21h /ethmac/tags/rel_23/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7781d 22h /ethmac/tags/rel_23/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7781d 22h /ethmac/tags/rel_23/rtl/verilog/
276 Defer indication changed. tadejm 7781d 22h /ethmac/tags/rel_23/rtl/verilog/
275 Fix MTxErr or prevent sending too big frames. mohor 7789d 03h /ethmac/tags/rel_23/rtl/verilog/
272 When control packets were received, they were ignored in some cases. tadejm 7789d 22h /ethmac/tags/rel_23/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7791d 00h /ethmac/tags/rel_23/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7792d 00h /ethmac/tags/rel_23/rtl/verilog/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7850d 22h /ethmac/tags/rel_23/rtl/verilog/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7851d 10h /ethmac/tags/rel_23/rtl/verilog/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7852d 11h /ethmac/tags/rel_23/rtl/verilog/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7852d 12h /ethmac/tags/rel_23/rtl/verilog/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7852d 12h /ethmac/tags/rel_23/rtl/verilog/
255 TPauseRq synchronized to tx_clk. mohor 7852d 12h /ethmac/tags/rel_23/rtl/verilog/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7853d 18h /ethmac/tags/rel_23/rtl/verilog/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7853d 18h /ethmac/tags/rel_23/rtl/verilog/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7853d 18h /ethmac/tags/rel_23/rtl/verilog/
248 wb_rst_i is used for MIIM reset. mohor 7854d 18h /ethmac/tags/rel_23/rtl/verilog/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7857d 21h /ethmac/tags/rel_23/rtl/verilog/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7858d 17h /ethmac/tags/rel_23/rtl/verilog/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7859d 13h /ethmac/tags/rel_23/rtl/verilog/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7859d 13h /ethmac/tags/rel_23/rtl/verilog/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7859d 13h /ethmac/tags/rel_23/rtl/verilog/

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