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[/] [ethmac/] [tags/] [rel_23/] [rtl/] [verilog/] - Rev 338

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Rev Log message Author Age Path
338 root 5470d 03h /ethmac/tags/rel_23/rtl/verilog/
335 New directory structure. root 5527d 09h /ethmac/tags/rel_23/rtl/verilog/
305 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7471d 00h /ethmac/tags/rel_23/rtl/verilog/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7471d 00h /ethmac/tags/rel_23/rtl/verilog/
302 mbist signals updated according to newest convention markom 7497d 11h /ethmac/tags/rel_23/rtl/verilog/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7508d 03h /ethmac/tags/rel_23/rtl/verilog/
297 Artisan ram instance added. simons 7561d 02h /ethmac/tags/rel_23/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 7597d 04h /ethmac/tags/rel_23/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7623d 07h /ethmac/tags/rel_23/rtl/verilog/
285 Binary operator used instead of unary (xnor). mohor 7623d 07h /ethmac/tags/rel_23/rtl/verilog/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7651d 09h /ethmac/tags/rel_23/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7679d 02h /ethmac/tags/rel_23/rtl/verilog/
280 Reset has priority in some flipflops. mohor 7757d 04h /ethmac/tags/rel_23/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7757d 05h /ethmac/tags/rel_23/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7757d 05h /ethmac/tags/rel_23/rtl/verilog/
276 Defer indication changed. tadejm 7757d 05h /ethmac/tags/rel_23/rtl/verilog/
275 Fix MTxErr or prevent sending too big frames. mohor 7764d 09h /ethmac/tags/rel_23/rtl/verilog/
272 When control packets were received, they were ignored in some cases. tadejm 7765d 05h /ethmac/tags/rel_23/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7766d 07h /ethmac/tags/rel_23/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7767d 07h /ethmac/tags/rel_23/rtl/verilog/

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