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Rev Log message Author Age Path
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7870d 08h /ethmac/tags/rel_24/
225 Some minor changes. tadejm 7870d 08h /ethmac/tags/rel_24/
224 Signals for a wave window in Modelsim. tadejm 7870d 09h /ethmac/tags/rel_24/
223 Some code changed due to bug fixes. tadejm 7870d 09h /ethmac/tags/rel_24/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7874d 07h /ethmac/tags/rel_24/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7877d 08h /ethmac/tags/rel_24/
218 Typo error fixed. (When using Bist) mohor 7877d 10h /ethmac/tags/rel_24/
217 Bist supported. mohor 7877d 10h /ethmac/tags/rel_24/
216 Bist signals added. mohor 7877d 10h /ethmac/tags/rel_24/
215 Bist supported. mohor 7877d 11h /ethmac/tags/rel_24/
214 Signals for WISHBONE B3 compliant interface added. mohor 7878d 06h /ethmac/tags/rel_24/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7878d 06h /ethmac/tags/rel_24/
212 Minor $display change. mohor 7878d 06h /ethmac/tags/rel_24/
211 Bist added. mohor 7878d 07h /ethmac/tags/rel_24/
210 BIST added. mohor 7878d 07h /ethmac/tags/rel_24/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7879d 10h /ethmac/tags/rel_24/
208 Virtual Silicon RAMs moved to lib directory tadej 7895d 04h /ethmac/tags/rel_24/
207 Virtual Silicon RAM support fixed tadej 7895d 04h /ethmac/tags/rel_24/
206 Virtual Silicon RAM added to the simulation. mohor 7895d 04h /ethmac/tags/rel_24/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7895d 05h /ethmac/tags/rel_24/

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