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Rev Log message Author Age Path
232 fpga define added. mohor 7844d 22h /ethmac/tags/rel_24/
231 Description of Core Modules added (figure). mohor 7846d 23h /ethmac/tags/rel_24/
229 case changed to casex. mohor 7850d 20h /ethmac/tags/rel_24/
227 Changed BIST scan signals. tadejm 7851d 00h /ethmac/tags/rel_24/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7851d 01h /ethmac/tags/rel_24/
225 Some minor changes. tadejm 7851d 01h /ethmac/tags/rel_24/
224 Signals for a wave window in Modelsim. tadejm 7851d 03h /ethmac/tags/rel_24/
223 Some code changed due to bug fixes. tadejm 7851d 03h /ethmac/tags/rel_24/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7855d 01h /ethmac/tags/rel_24/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7858d 01h /ethmac/tags/rel_24/
218 Typo error fixed. (When using Bist) mohor 7858d 03h /ethmac/tags/rel_24/
217 Bist supported. mohor 7858d 03h /ethmac/tags/rel_24/
216 Bist signals added. mohor 7858d 03h /ethmac/tags/rel_24/
215 Bist supported. mohor 7858d 04h /ethmac/tags/rel_24/
214 Signals for WISHBONE B3 compliant interface added. mohor 7859d 00h /ethmac/tags/rel_24/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7859d 00h /ethmac/tags/rel_24/
212 Minor $display change. mohor 7859d 00h /ethmac/tags/rel_24/
211 Bist added. mohor 7859d 00h /ethmac/tags/rel_24/
210 BIST added. mohor 7859d 00h /ethmac/tags/rel_24/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7860d 04h /ethmac/tags/rel_24/

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