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241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7834d 21h /ethmac/tags/rel_24/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7834d 21h /ethmac/tags/rel_24/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7834d 21h /ethmac/tags/rel_24/
238 Defines fixed to use generic RAM by default. mohor 7847d 01h /ethmac/tags/rel_24/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7849d 07h /ethmac/tags/rel_24/
235 rev 4. mohor 7849d 21h /ethmac/tags/rel_24/
234 Figure list assed to the revision 3. mohor 7850d 06h /ethmac/tags/rel_24/
233 Revision 0.3 released. Some figures added. mohor 7850d 06h /ethmac/tags/rel_24/
232 fpga define added. mohor 7855d 01h /ethmac/tags/rel_24/
231 Description of Core Modules added (figure). mohor 7857d 02h /ethmac/tags/rel_24/
229 case changed to casex. mohor 7860d 23h /ethmac/tags/rel_24/
227 Changed BIST scan signals. tadejm 7861d 03h /ethmac/tags/rel_24/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7861d 04h /ethmac/tags/rel_24/
225 Some minor changes. tadejm 7861d 04h /ethmac/tags/rel_24/
224 Signals for a wave window in Modelsim. tadejm 7861d 06h /ethmac/tags/rel_24/
223 Some code changed due to bug fixes. tadejm 7861d 06h /ethmac/tags/rel_24/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7865d 04h /ethmac/tags/rel_24/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7868d 04h /ethmac/tags/rel_24/
218 Typo error fixed. (When using Bist) mohor 7868d 06h /ethmac/tags/rel_24/
217 Bist supported. mohor 7868d 06h /ethmac/tags/rel_24/
216 Bist signals added. mohor 7868d 06h /ethmac/tags/rel_24/
215 Bist supported. mohor 7868d 07h /ethmac/tags/rel_24/
214 Signals for WISHBONE B3 compliant interface added. mohor 7869d 03h /ethmac/tags/rel_24/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7869d 03h /ethmac/tags/rel_24/
212 Minor $display change. mohor 7869d 03h /ethmac/tags/rel_24/
211 Bist added. mohor 7869d 03h /ethmac/tags/rel_24/
210 BIST added. mohor 7869d 03h /ethmac/tags/rel_24/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7870d 06h /ethmac/tags/rel_24/
208 Virtual Silicon RAMs moved to lib directory tadej 7886d 00h /ethmac/tags/rel_24/
207 Virtual Silicon RAM support fixed tadej 7886d 00h /ethmac/tags/rel_24/

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