OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_24/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 338

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 5472d 02h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
335 New directory structure. root 5529d 07h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7451d 02h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
276 Defer indication changed. tadejm 7759d 04h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7828d 15h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7836d 19h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7899d 02h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7906d 23h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
126 InvalidSymbol generation changed. mohor 7947d 23h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8042d 03h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
70 Small fixes. mohor 8105d 07h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8108d 00h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
43 Tx status is written back to the BD. mohor 8112d 08h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
42 Rx status is written back to the BD. mohor 8115d 01h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
37 Link in the header changed. mohor 8131d 07h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8227d 09h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
18 Few little NCSIM warnings fixed. mohor 8265d 03h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8301d 03h /ethmac/tags/rel_24/rtl/verilog/eth_macstatus.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.