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[/] [ethmac/] [tags/] [rel_24/] [rtl/] [verilog/] [eth_registers.v] - Rev 307

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307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7472d 06h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7494d 03h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7702d 05h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7849d 19h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7852d 03h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7857d 03h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
164 Ethernet debug registers removed. mohor 7922d 11h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.		 mohor 7928d 03h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.		 mohor 7944d 05h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
141 Syntax error fixed. mohor 7946d 23h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
140 Syntax error fixed. mohor 7946d 23h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.		 mohor 7946d 23h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7949d 03h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8063d 07h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
74 Reset values are passed to registers through parameters mohor 8118d 05h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
69 Define missmatch fixed. mohor 8127d 08h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 8128d 07h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 8129d 10h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8130d 01h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v
46 HASH0 and HASH1 registers added. mohor 8132d 04h /ethmac/tags/rel_24/rtl/verilog/eth_registers.v

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