URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_24/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 335

Rev	Log message	Author	Age	Path
335	New directory structure.	root	5544d 08h	/ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
307	This commit was manufactured by cvs2svn to create tag 'rel_24'.		7466d 04h	/ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
306	Lapsus fixed (!we -> ~we).	simons	7466d 04h	/ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7488d 00h	/ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
302	mbist signals updated according to newest convention	markom	7514d 11h	/ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
297	Artisan ram instance added.	simons	7578d 02h	/ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
227	Changed BIST scan signals.	tadejm	7878d 01h	/ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
210	BIST added.	mohor	7886d 02h	/ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7903d 00h	/ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7965d 02h	/ethmac/tags/rel_24/rtl/verilog/eth_spram_256x32.v