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Rev Log message Author Age Path
245 Rev 1.7. mohor 7840d 14h /ethmac/tags/rel_24
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7840d 16h /ethmac/tags/rel_24
243 Late collision is not reported any more. tadejm 7840d 22h /ethmac/tags/rel_24
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7841d 13h /ethmac/tags/rel_24
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7841d 13h /ethmac/tags/rel_24
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7841d 13h /ethmac/tags/rel_24
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7841d 13h /ethmac/tags/rel_24
238 Defines fixed to use generic RAM by default. mohor 7853d 17h /ethmac/tags/rel_24
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7855d 22h /ethmac/tags/rel_24
235 rev 4. mohor 7856d 13h /ethmac/tags/rel_24
234 Figure list assed to the revision 3. mohor 7856d 21h /ethmac/tags/rel_24
233 Revision 0.3 released. Some figures added. mohor 7856d 21h /ethmac/tags/rel_24
232 fpga define added. mohor 7861d 16h /ethmac/tags/rel_24
231 Description of Core Modules added (figure). mohor 7863d 18h /ethmac/tags/rel_24
229 case changed to casex. mohor 7867d 14h /ethmac/tags/rel_24
227 Changed BIST scan signals. tadejm 7867d 18h /ethmac/tags/rel_24
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7867d 19h /ethmac/tags/rel_24
225 Some minor changes. tadejm 7867d 20h /ethmac/tags/rel_24
224 Signals for a wave window in Modelsim. tadejm 7867d 21h /ethmac/tags/rel_24
223 Some code changed due to bug fixes. tadejm 7867d 21h /ethmac/tags/rel_24

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