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[/] [ethmac/] [tags/] [rel_25/] - Rev 248

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248 wb_rst_i is used for MIIM reset. mohor 7852d 14h /ethmac/tags/rel_25
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7855d 17h /ethmac/tags/rel_25
245 Rev 1.7. mohor 7856d 11h /ethmac/tags/rel_25
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7856d 13h /ethmac/tags/rel_25
243 Late collision is not reported any more. tadejm 7856d 18h /ethmac/tags/rel_25
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7857d 09h /ethmac/tags/rel_25
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7857d 09h /ethmac/tags/rel_25
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7857d 09h /ethmac/tags/rel_25
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7857d 09h /ethmac/tags/rel_25
238 Defines fixed to use generic RAM by default. mohor 7869d 13h /ethmac/tags/rel_25
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7871d 19h /ethmac/tags/rel_25
235 rev 4. mohor 7872d 09h /ethmac/tags/rel_25
234 Figure list assed to the revision 3. mohor 7872d 17h /ethmac/tags/rel_25
233 Revision 0.3 released. Some figures added. mohor 7872d 18h /ethmac/tags/rel_25
232 fpga define added. mohor 7877d 13h /ethmac/tags/rel_25
231 Description of Core Modules added (figure). mohor 7879d 14h /ethmac/tags/rel_25
229 case changed to casex. mohor 7883d 11h /ethmac/tags/rel_25
227 Changed BIST scan signals. tadejm 7883d 14h /ethmac/tags/rel_25
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7883d 16h /ethmac/tags/rel_25
225 Some minor changes. tadejm 7883d 16h /ethmac/tags/rel_25
224 Signals for a wave window in Modelsim. tadejm 7883d 17h /ethmac/tags/rel_25
223 Some code changed due to bug fixes. tadejm 7883d 18h /ethmac/tags/rel_25
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7887d 15h /ethmac/tags/rel_25
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7890d 16h /ethmac/tags/rel_25
218 Typo error fixed. (When using Bist) mohor 7890d 18h /ethmac/tags/rel_25
217 Bist supported. mohor 7890d 18h /ethmac/tags/rel_25
216 Bist signals added. mohor 7890d 18h /ethmac/tags/rel_25
215 Bist supported. mohor 7890d 19h /ethmac/tags/rel_25
214 Signals for WISHBONE B3 compliant interface added. mohor 7891d 15h /ethmac/tags/rel_25
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7891d 15h /ethmac/tags/rel_25

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