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[/] [ethmac/] [tags/] [rel_25/] - Rev 270

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270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7789d 03h /ethmac/tags/rel_25
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7790d 03h /ethmac/tags/rel_25
268 Release 1.19. Control frame description changed. mohor 7843d 21h /ethmac/tags/rel_25
267 Full duplex control frames tested. mohor 7843d 23h /ethmac/tags/rel_25
266 Flow control test almost finished. mohor 7848d 22h /ethmac/tags/rel_25
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7849d 02h /ethmac/tags/rel_25
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7849d 13h /ethmac/tags/rel_25
262 Version 1.18 released.
MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER
register. Control Frame bit (CF) added to the RX buffer descriptor. Control
frame detection section updated.		 mohor 7849d 13h /ethmac/tags/rel_25
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7849d 13h /ethmac/tags/rel_25
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7850d 01h /ethmac/tags/rel_25
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7850d 15h /ethmac/tags/rel_25
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7850d 15h /ethmac/tags/rel_25
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7850d 15h /ethmac/tags/rel_25
255 TPauseRq synchronized to tx_clk. mohor 7850d 15h /ethmac/tags/rel_25
254 Temp version. mohor 7851d 19h /ethmac/tags/rel_25
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7851d 21h /ethmac/tags/rel_25
252 Just some updates. tadejm 7851d 22h /ethmac/tags/rel_25
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7851d 22h /ethmac/tags/rel_25
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7851d 22h /ethmac/tags/rel_25
248 wb_rst_i is used for MIIM reset. mohor 7852d 22h /ethmac/tags/rel_25
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7856d 01h /ethmac/tags/rel_25
245 Rev 1.7. mohor 7856d 19h /ethmac/tags/rel_25
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7856d 21h /ethmac/tags/rel_25
243 Late collision is not reported any more. tadejm 7857d 02h /ethmac/tags/rel_25
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7857d 17h /ethmac/tags/rel_25
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7857d 17h /ethmac/tags/rel_25
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7857d 17h /ethmac/tags/rel_25
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7857d 17h /ethmac/tags/rel_25
238 Defines fixed to use generic RAM by default. mohor 7869d 21h /ethmac/tags/rel_25
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7872d 03h /ethmac/tags/rel_25

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