OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_25/] [bench/] [verilog/] - Rev 188

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
188 PHY changed. tadej 7901d 16h /ethmac/tags/rel_25/bench/verilog/
182 Full duplex test improved. tadej 7902d 19h /ethmac/tags/rel_25/bench/verilog/
181 MIIM test look better. mohor 7902d 21h /ethmac/tags/rel_25/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7905d 17h /ethmac/tags/rel_25/bench/verilog/
179 Beautiful tests merget together mohor 7905d 18h /ethmac/tags/rel_25/bench/verilog/
178 Rearanged testcases mohor 7905d 18h /ethmac/tags/rel_25/bench/verilog/
177 Bug in MIIM fixed. mohor 7905d 22h /ethmac/tags/rel_25/bench/verilog/
170 Headers changed. mohor 7906d 00h /ethmac/tags/rel_25/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7906d 01h /ethmac/tags/rel_25/bench/verilog/
158 Typo fixed. mohor 7910d 20h /ethmac/tags/rel_25/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7913d 01h /ethmac/tags/rel_25/bench/verilog/
156 Valid testbench. mohor 7913d 01h /ethmac/tags/rel_25/bench/verilog/
155 Minor changes. mohor 7913d 02h /ethmac/tags/rel_25/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7955d 19h /ethmac/tags/rel_25/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7957d 20h /ethmac/tags/rel_25/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 7961d 23h /ethmac/tags/rel_25/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7961d 23h /ethmac/tags/rel_25/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8039d 02h /ethmac/tags/rel_25/bench/verilog/
107 TX_BUF_BASE changed. mohor 8039d 02h /ethmac/tags/rel_25/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8084d 00h /ethmac/tags/rel_25/bench/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.