OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_25/] [bench/] [verilog/] - Rev 227

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
155 Minor changes. mohor 7914d 08h /ethmac/tags/rel_25/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7957d 02h /ethmac/tags/rel_25/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7959d 02h /ethmac/tags/rel_25/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 7963d 05h /ethmac/tags/rel_25/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 7963d 05h /ethmac/tags/rel_25/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8040d 09h /ethmac/tags/rel_25/bench/verilog/
107 TX_BUF_BASE changed. mohor 8040d 09h /ethmac/tags/rel_25/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 8085d 06h /ethmac/tags/rel_25/bench/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 8106d 02h /ethmac/tags/rel_25/bench/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8116d 06h /ethmac/tags/rel_25/bench/verilog/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.