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Rev Log message Author Age Path
245 Rev 1.7. mohor 7841d 22h /ethmac/tags/rel_26/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7842d 00h /ethmac/tags/rel_26/
243 Late collision is not reported any more. tadejm 7842d 05h /ethmac/tags/rel_26/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7842d 20h /ethmac/tags/rel_26/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7842d 20h /ethmac/tags/rel_26/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7842d 20h /ethmac/tags/rel_26/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7842d 20h /ethmac/tags/rel_26/
238 Defines fixed to use generic RAM by default. mohor 7855d 00h /ethmac/tags/rel_26/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7857d 05h /ethmac/tags/rel_26/
235 rev 4. mohor 7857d 20h /ethmac/tags/rel_26/
234 Figure list assed to the revision 3. mohor 7858d 04h /ethmac/tags/rel_26/
233 Revision 0.3 released. Some figures added. mohor 7858d 05h /ethmac/tags/rel_26/
232 fpga define added. mohor 7863d 00h /ethmac/tags/rel_26/
231 Description of Core Modules added (figure). mohor 7865d 01h /ethmac/tags/rel_26/
229 case changed to casex. mohor 7868d 22h /ethmac/tags/rel_26/
227 Changed BIST scan signals. tadejm 7869d 01h /ethmac/tags/rel_26/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7869d 03h /ethmac/tags/rel_26/
225 Some minor changes. tadejm 7869d 03h /ethmac/tags/rel_26/
224 Signals for a wave window in Modelsim. tadejm 7869d 04h /ethmac/tags/rel_26/
223 Some code changed due to bug fixes. tadejm 7869d 04h /ethmac/tags/rel_26/

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