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[/] [ethmac/] [tags/] [rel_26/] [bench/] - Rev 157

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Rev Log message Author Age Path
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 7044d 01h /ethmac/tags/rel_26/bench/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7053d 00h /ethmac/tags/rel_26/bench/
12 Directory structure changed. Files checked and joind together. mohor 7059d 17h /ethmac/tags/rel_26/bench/

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