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[/] [ethmac/] [tags/] [rel_26/] [rtl/] [verilog/] [eth_top.v] - Rev 338

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338 root 5480d 13h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
335 New directory structure. root 5537d 18h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
322 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7315d 13h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7315d 13h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7481d 10h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
302 mbist signals updated according to newest convention markom 7507d 20h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7518d 12h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
276 Defer indication changed. tadejm 7767d 14h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
272 When control packets were received, they were ignored in some cases. tadejm 7775d 14h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7776d 16h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7837d 02h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
255 TPauseRq synchronized to tx_clk. mohor 7838d 04h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7839d 10h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7839d 10h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
248 wb_rst_i is used for MIIM reset. mohor 7840d 10h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7844d 09h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7845d 06h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
227 Changed BIST scan signals. tadejm 7871d 11h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
218 Typo error fixed. (When using Bist) mohor 7878d 14h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
214 Signals for WISHBONE B3 compliant interface added. mohor 7879d 11h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
210 BIST added. mohor 7879d 11h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7899d 11h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7907d 13h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
164 Ethernet debug registers removed. mohor 7909d 17h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7910d 15h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7915d 09h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7956d 10h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7964d 09h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8039d 18h /ethmac/tags/rel_26/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8050d 14h /ethmac/tags/rel_26/rtl/verilog/eth_top.v

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