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[/] [ethmac/] [tags/] [rel_26/] [rtl] - Rev 227

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Rev Log message Author Age Path
227 Changed BIST scan signals. tadejm 7866d 17h /ethmac/tags/rel_26/rtl
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7866d 18h /ethmac/tags/rel_26/rtl
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7870d 18h /ethmac/tags/rel_26/rtl
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7873d 18h /ethmac/tags/rel_26/rtl
218 Typo error fixed. (When using Bist) mohor 7873d 20h /ethmac/tags/rel_26/rtl
214 Signals for WISHBONE B3 compliant interface added. mohor 7874d 17h /ethmac/tags/rel_26/rtl
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7874d 17h /ethmac/tags/rel_26/rtl
212 Minor $display change. mohor 7874d 17h /ethmac/tags/rel_26/rtl
211 Bist added. mohor 7874d 18h /ethmac/tags/rel_26/rtl
210 BIST added. mohor 7874d 18h /ethmac/tags/rel_26/rtl
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7891d 16h /ethmac/tags/rel_26/rtl
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7891d 16h /ethmac/tags/rel_26/rtl
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7894d 17h /ethmac/tags/rel_26/rtl
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7902d 19h /ethmac/tags/rel_26/rtl
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7903d 20h /ethmac/tags/rel_26/rtl
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7904d 20h /ethmac/tags/rel_26/rtl
165 HASH improvement needed. mohor 7904d 23h /ethmac/tags/rel_26/rtl
164 Ethernet debug registers removed. mohor 7904d 23h /ethmac/tags/rel_26/rtl
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7905d 21h /ethmac/tags/rel_26/rtl
160 error acknowledge cycle termination added to display. mohor 7905d 21h /ethmac/tags/rel_26/rtl

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