URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_26/] [sim/] - Rev 310

Rev	Log message	Author	Age	Path
310	More signals.	tadejm	7449d 04h	/ethmac/tags/rel_26/sim
309	Update file list files for different RAM models with byte select accessing.	tadejm	7449d 04h	/ethmac/tags/rel_26/sim
308	Moved RAM model file path from sim_file_list.lst to this file.	tadejm	7449d 04h	/ethmac/tags/rel_26/sim
299	Artisan RAMs added.	mohor	7556d 05h	/ethmac/tags/rel_26/sim
295	Few minor changes.	tadejm	7563d 03h	/ethmac/tags/rel_26/sim
294	Added path to a file with distributed RAM instances for xilinx.	tadejm	7565d 04h	/ethmac/tags/rel_26/sim
293	initial.	tadejm	7589d 01h	/ethmac/tags/rel_26/sim
292	Corrected mistake.	tadejm	7589d 01h	/ethmac/tags/rel_26/sim
291	initial	tadejm	7589d 02h	/ethmac/tags/rel_26/sim
290	Additional checking for FAILED tests added - for ATS.	tadejm	7589d 03h	/ethmac/tags/rel_26/sim
225	Some minor changes.	tadejm	7862d 01h	/ethmac/tags/rel_26/sim
224	Signals for a wave window in Modelsim.	tadejm	7862d 03h	/ethmac/tags/rel_26/sim
217	Bist supported.	mohor	7869d 03h	/ethmac/tags/rel_26/sim
215	Bist supported.	mohor	7869d 04h	/ethmac/tags/rel_26/sim
208	Virtual Silicon RAMs moved to lib directory	tadej	7886d 22h	/ethmac/tags/rel_26/sim
207	Virtual Silicon RAM support fixed	tadej	7886d 22h	/ethmac/tags/rel_26/sim
206	Virtual Silicon RAM added to the simulation.	mohor	7886d 22h	/ethmac/tags/rel_26/sim
205	ETH_VIRTUAL_SILICON_RAM supported.	mohor	7886d 23h	/ethmac/tags/rel_26/sim
187	_info file added.	mohor	7892d 21h	/ethmac/tags/rel_26/sim
186	Macro for testbench (DO file).	mohor	7892d 22h	/ethmac/tags/rel_26/sim