OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_26/] [sim/] - Rev 311

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
311 Update script for running different file list files for different RAM models. tadejm 7448d 08h /ethmac/tags/rel_26/sim/
310 More signals. tadejm 7448d 09h /ethmac/tags/rel_26/sim/
309 Update file list files for different RAM models with byte select accessing. tadejm 7448d 09h /ethmac/tags/rel_26/sim/
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 7448d 09h /ethmac/tags/rel_26/sim/
299 Artisan RAMs added. mohor 7555d 09h /ethmac/tags/rel_26/sim/
295 Few minor changes. tadejm 7562d 07h /ethmac/tags/rel_26/sim/
294 Added path to a file with distributed RAM instances for xilinx. tadejm 7564d 08h /ethmac/tags/rel_26/sim/
293 initial. tadejm 7588d 05h /ethmac/tags/rel_26/sim/
292 Corrected mistake. tadejm 7588d 05h /ethmac/tags/rel_26/sim/
291 initial tadejm 7588d 06h /ethmac/tags/rel_26/sim/
290 Additional checking for FAILED tests added - for ATS. tadejm 7588d 07h /ethmac/tags/rel_26/sim/
225 Some minor changes. tadejm 7861d 06h /ethmac/tags/rel_26/sim/
224 Signals for a wave window in Modelsim. tadejm 7861d 07h /ethmac/tags/rel_26/sim/
217 Bist supported. mohor 7868d 08h /ethmac/tags/rel_26/sim/
215 Bist supported. mohor 7868d 08h /ethmac/tags/rel_26/sim/
208 Virtual Silicon RAMs moved to lib directory tadej 7886d 02h /ethmac/tags/rel_26/sim/
207 Virtual Silicon RAM support fixed tadej 7886d 02h /ethmac/tags/rel_26/sim/
206 Virtual Silicon RAM added to the simulation. mohor 7886d 02h /ethmac/tags/rel_26/sim/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7886d 03h /ethmac/tags/rel_26/sim/
187 _info file added. mohor 7892d 01h /ethmac/tags/rel_26/sim/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.