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[/] [ethmac/] [tags/] [rel_27/] - Rev 15

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15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 8308d 11h /ethmac/tags/rel_27/
14 Unconnected signals are now connected. mohor 8312d 17h /ethmac/tags/rel_27/
13 New directory structure. Files upodated and put together. mohor 8315d 02h /ethmac/tags/rel_27/
12 Directory structure changed. Files checked and joind together. mohor 8315d 04h /ethmac/tags/rel_27/
11 Directory structure changed. Files checked and joind together. mohor 8315d 05h /ethmac/tags/rel_27/
10 Directory structure changed. Files checked and joind together. mohor 8315d 05h /ethmac/tags/rel_27/
9 Documentation updated to be synchronized to the verilog files. mohor 8342d 13h /ethmac/tags/rel_27/
8 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.
mohor 8369d 18h /ethmac/tags/rel_27/
7 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.
mohor 8369d 18h /ethmac/tags/rel_27/
6 no message mohor 8369d 18h /ethmac/tags/rel_27/
5 This is a Microsoft version of the spec in the pdf format. mohor 8374d 04h /ethmac/tags/rel_27/
4 deleted mohor 8374d 04h /ethmac/tags/rel_27/
2 no message mohor 8446d 04h /ethmac/tags/rel_27/
1 Standard project directories initialized by cvs2svn. 8446d 04h /ethmac/tags/rel_27/

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