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Rev Log message Author Age Path
180 Bench outputs data to display every 128 bytes. mohor 8042d 01h /ethmac/tags/rel_27/
179 Beautiful tests merget together mohor 8042d 01h /ethmac/tags/rel_27/
178 Rearanged testcases mohor 8042d 01h /ethmac/tags/rel_27/
177 Bug in MIIM fixed. mohor 8042d 05h /ethmac/tags/rel_27/
176 lists changed to new directory structure mohor 8042d 07h /ethmac/tags/rel_27/
175 Script fixed to new dir structure mohor 8042d 07h /ethmac/tags/rel_27/
174 Directory keeper mohor 8042d 07h /ethmac/tags/rel_27/
173 Keeps the directory mohor 8042d 07h /ethmac/tags/rel_27/
172 NCSIM simulation environment added to cvs mohor 8042d 07h /ethmac/tags/rel_27/
171 NCSIM simulation environment added. mohor 8042d 07h /ethmac/tags/rel_27/
170 Headers changed. mohor 8042d 08h /ethmac/tags/rel_27/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 8042d 08h /ethmac/tags/rel_27/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 8043d 05h /ethmac/tags/rel_27/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 8044d 06h /ethmac/tags/rel_27/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 8045d 06h /ethmac/tags/rel_27/
165 HASH improvement needed. mohor 8045d 09h /ethmac/tags/rel_27/
164 Ethernet debug registers removed. mohor 8045d 10h /ethmac/tags/rel_27/
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 8046d 01h /ethmac/tags/rel_27/
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 8046d 01h /ethmac/tags/rel_27/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 8046d 07h /ethmac/tags/rel_27/

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