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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7870d 02h /ethmac/tags/rel_27/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7873d 02h /ethmac/tags/rel_27/
218 Typo error fixed. (When using Bist) mohor 7873d 04h /ethmac/tags/rel_27/
217 Bist supported. mohor 7873d 04h /ethmac/tags/rel_27/
216 Bist signals added. mohor 7873d 04h /ethmac/tags/rel_27/
215 Bist supported. mohor 7873d 05h /ethmac/tags/rel_27/
214 Signals for WISHBONE B3 compliant interface added. mohor 7874d 01h /ethmac/tags/rel_27/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7874d 01h /ethmac/tags/rel_27/
212 Minor $display change. mohor 7874d 01h /ethmac/tags/rel_27/
211 Bist added. mohor 7874d 01h /ethmac/tags/rel_27/
210 BIST added. mohor 7874d 01h /ethmac/tags/rel_27/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7875d 04h /ethmac/tags/rel_27/
208 Virtual Silicon RAMs moved to lib directory tadej 7890d 22h /ethmac/tags/rel_27/
207 Virtual Silicon RAM support fixed tadej 7890d 22h /ethmac/tags/rel_27/
206 Virtual Silicon RAM added to the simulation. mohor 7890d 23h /ethmac/tags/rel_27/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7890d 23h /ethmac/tags/rel_27/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7890d 23h /ethmac/tags/rel_27/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7890d 23h /ethmac/tags/rel_27/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7894d 00h /ethmac/tags/rel_27/
201 Core size added to the document. mohor 7894d 01h /ethmac/tags/rel_27/

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