URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 182

Rev	Log message	Author	Age	Path
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8109d 06h	/ethmac/tags/rel_27/bench/verilog/
66	Testbench fixed, code simplified, unused signals removed.	mohor	8109d 12h	/ethmac/tags/rel_27/bench/verilog/
51	Added separate tests for Multicast, Unicast, Broadcast	billditt	8110d 23h	/ethmac/tags/rel_27/bench/verilog/
49	HASH0 and HASH1 register read/write added.	mohor	8112d 23h	/ethmac/tags/rel_27/bench/verilog/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8119d 05h	/ethmac/tags/rel_27/bench/verilog/
36	TX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8179d 07h	/ethmac/tags/rel_27/bench/verilog/
23	Number of addresses (wb_adr_i) minimized.	mohor	8229d 08h	/ethmac/tags/rel_27/bench/verilog/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8229d 10h	/ethmac/tags/rel_27/bench/verilog/
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8254d 04h	/ethmac/tags/rel_27/bench/verilog/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8294d 05h	/ethmac/tags/rel_27/bench/verilog/