URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 209

Rev	Log message	Author	Age	Path
117	Clock mrx_clk set to 2.5 MHz.	mohor	7983d 22h	/ethmac/tags/rel_27/bench/verilog
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	7983d 22h	/ethmac/tags/rel_27/bench/verilog
108	Testbench supports unaligned accesses.	mohor	8061d 01h	/ethmac/tags/rel_27/bench/verilog
107	TX_BUF_BASE changed.	mohor	8061d 01h	/ethmac/tags/rel_27/bench/verilog
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8105d 23h	/ethmac/tags/rel_27/bench/verilog
80	Small fixes for external/internal DMA missmatches.	mohor	8126d 19h	/ethmac/tags/rel_27/bench/verilog
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8136d 22h	/ethmac/tags/rel_27/bench/verilog
66	Testbench fixed, code simplified, unused signals removed.	mohor	8137d 04h	/ethmac/tags/rel_27/bench/verilog
51	Added separate tests for Multicast, Unicast, Broadcast	billditt	8138d 15h	/ethmac/tags/rel_27/bench/verilog
49	HASH0 and HASH1 register read/write added.	mohor	8140d 15h	/ethmac/tags/rel_27/bench/verilog