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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 216

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Rev Log message Author Age Path
216 Bist signals added. mohor 6590d 14h /ethmac/tags/rel_27/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6592d 14h /ethmac/tags/rel_27/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 6611d 13h /ethmac/tags/rel_27/bench/verilog/
192 Some additional reports added tadej 6613d 09h /ethmac/tags/rel_27/bench/verilog/
191 Bug repaired in eth_phy device tadej 6613d 09h /ethmac/tags/rel_27/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 6613d 11h /ethmac/tags/rel_27/bench/verilog/
188 PHY changed. tadej 6614d 07h /ethmac/tags/rel_27/bench/verilog/
182 Full duplex test improved. tadej 6615d 09h /ethmac/tags/rel_27/bench/verilog/
181 MIIM test look better. mohor 6615d 12h /ethmac/tags/rel_27/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 6618d 08h /ethmac/tags/rel_27/bench/verilog/
179 Beautiful tests merget together mohor 6618d 09h /ethmac/tags/rel_27/bench/verilog/
178 Rearanged testcases mohor 6618d 09h /ethmac/tags/rel_27/bench/verilog/
177 Bug in MIIM fixed. mohor 6618d 12h /ethmac/tags/rel_27/bench/verilog/
170 Headers changed. mohor 6618d 15h /ethmac/tags/rel_27/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 6618d 15h /ethmac/tags/rel_27/bench/verilog/
158 Typo fixed. mohor 6623d 11h /ethmac/tags/rel_27/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 6625d 16h /ethmac/tags/rel_27/bench/verilog/
156 Valid testbench. mohor 6625d 16h /ethmac/tags/rel_27/bench/verilog/
155 Minor changes. mohor 6625d 16h /ethmac/tags/rel_27/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6668d 10h /ethmac/tags/rel_27/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6670d 11h /ethmac/tags/rel_27/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 6674d 13h /ethmac/tags/rel_27/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 6674d 13h /ethmac/tags/rel_27/bench/verilog/
108 Testbench supports unaligned accesses. mohor 6751d 17h /ethmac/tags/rel_27/bench/verilog/
107 TX_BUF_BASE changed. mohor 6751d 17h /ethmac/tags/rel_27/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 6796d 14h /ethmac/tags/rel_27/bench/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 6817d 10h /ethmac/tags/rel_27/bench/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 6827d 14h /ethmac/tags/rel_27/bench/verilog/
66 Testbench fixed, code simplified, unused signals removed. mohor 6827d 20h /ethmac/tags/rel_27/bench/verilog/
51 Added separate tests for Multicast, Unicast, Broadcast billditt 6829d 07h /ethmac/tags/rel_27/bench/verilog/

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