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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 227

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Rev Log message Author Age Path
227 Changed BIST scan signals. tadejm 7867d 00h /ethmac/tags/rel_27/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7867d 03h /ethmac/tags/rel_27/bench/verilog/
216 Bist signals added. mohor 7874d 03h /ethmac/tags/rel_27/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7876d 03h /ethmac/tags/rel_27/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7895d 02h /ethmac/tags/rel_27/bench/verilog/
192 Some additional reports added tadej 7896d 23h /ethmac/tags/rel_27/bench/verilog/
191 Bug repaired in eth_phy device tadej 7896d 23h /ethmac/tags/rel_27/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7897d 00h /ethmac/tags/rel_27/bench/verilog/
188 PHY changed. tadej 7897d 21h /ethmac/tags/rel_27/bench/verilog/
182 Full duplex test improved. tadej 7898d 23h /ethmac/tags/rel_27/bench/verilog/
181 MIIM test look better. mohor 7899d 02h /ethmac/tags/rel_27/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7901d 21h /ethmac/tags/rel_27/bench/verilog/
179 Beautiful tests merget together mohor 7901d 22h /ethmac/tags/rel_27/bench/verilog/
178 Rearanged testcases mohor 7901d 22h /ethmac/tags/rel_27/bench/verilog/
177 Bug in MIIM fixed. mohor 7902d 02h /ethmac/tags/rel_27/bench/verilog/
170 Headers changed. mohor 7902d 04h /ethmac/tags/rel_27/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7902d 05h /ethmac/tags/rel_27/bench/verilog/
158 Typo fixed. mohor 7907d 01h /ethmac/tags/rel_27/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7909d 06h /ethmac/tags/rel_27/bench/verilog/
156 Valid testbench. mohor 7909d 06h /ethmac/tags/rel_27/bench/verilog/
155 Minor changes. mohor 7909d 06h /ethmac/tags/rel_27/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7951d 23h /ethmac/tags/rel_27/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7954d 00h /ethmac/tags/rel_27/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 7958d 03h /ethmac/tags/rel_27/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7958d 03h /ethmac/tags/rel_27/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8035d 06h /ethmac/tags/rel_27/bench/verilog/
107 TX_BUF_BASE changed. mohor 8035d 06h /ethmac/tags/rel_27/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8080d 04h /ethmac/tags/rel_27/bench/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 8101d 00h /ethmac/tags/rel_27/bench/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8111d 04h /ethmac/tags/rel_27/bench/verilog/

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