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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 267

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Rev	Log message	Author	Age	Path
267	Full duplex control frames tested.	mohor	7835d 15h	/ethmac/tags/rel_27/bench/verilog
266	Flow control test almost finished.	mohor	7840d 14h	/ethmac/tags/rel_27/bench/verilog
263	test_mac_full_duplex_flow_control tests pretty much finished. TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) finished. TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps ) finished.	mohor	7841d 05h	/ethmac/tags/rel_27/bench/verilog
260	test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame finished.	mohor	7841d 17h	/ethmac/tags/rel_27/bench/verilog
254	Temp version.	mohor	7843d 11h	/ethmac/tags/rel_27/bench/verilog
252	Just some updates.	tadejm	7843d 14h	/ethmac/tags/rel_27/bench/verilog
243	Late collision is not reported any more.	tadejm	7848d 18h	/ethmac/tags/rel_27/bench/verilog
227	Changed BIST scan signals.	tadejm	7875d 14h	/ethmac/tags/rel_27/bench/verilog
223	Some code changed due to bug fixes.	tadejm	7875d 17h	/ethmac/tags/rel_27/bench/verilog
216	Bist signals added.	mohor	7882d 18h	/ethmac/tags/rel_27/bench/verilog
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	7884d 18h	/ethmac/tags/rel_27/bench/verilog
194	Full duplex tests modified and testbench bug repaired.	tadej	7903d 17h	/ethmac/tags/rel_27/bench/verilog
192	Some additional reports added	tadej	7905d 13h	/ethmac/tags/rel_27/bench/verilog
191	Bug repaired in eth_phy device	tadej	7905d 13h	/ethmac/tags/rel_27/bench/verilog
189	Simple testbench that includes eth_cop, eth_host and eth_memory modules. This testbench is used for testing the whole environment. Use tb_ethernet testbench for testing just the ethernet MAC core (many tests).	mohor	7905d 15h	/ethmac/tags/rel_27/bench/verilog
188	PHY changed.	tadej	7906d 11h	/ethmac/tags/rel_27/bench/verilog
182	Full duplex test improved.	tadej	7907d 13h	/ethmac/tags/rel_27/bench/verilog
181	MIIM test look better.	mohor	7907d 16h	/ethmac/tags/rel_27/bench/verilog
180	Bench outputs data to display every 128 bytes.	mohor	7910d 12h	/ethmac/tags/rel_27/bench/verilog
179	Beautiful tests merget together	mohor	7910d 13h	/ethmac/tags/rel_27/bench/verilog
178	Rearanged testcases	mohor	7910d 13h	/ethmac/tags/rel_27/bench/verilog
177	Bug in MIIM fixed.	mohor	7910d 16h	/ethmac/tags/rel_27/bench/verilog
170	Headers changed.	mohor	7910d 19h	/ethmac/tags/rel_27/bench/verilog
169	New testbench. Thanks to Tadej M - "The Spammer".	mohor	7910d 19h	/ethmac/tags/rel_27/bench/verilog
158	Typo fixed.	mohor	7915d 15h	/ethmac/tags/rel_27/bench/verilog
157	This testbench will soon be obsolete. Please use tb_ethernet.v	mohor	7917d 20h	/ethmac/tags/rel_27/bench/verilog
156	Valid testbench.	mohor	7917d 20h	/ethmac/tags/rel_27/bench/verilog
155	Minor changes.	mohor	7917d 20h	/ethmac/tags/rel_27/bench/verilog
124	Define ETH_MIIMODER_RST corrected to 0x00000400.	mohor	7960d 14h	/ethmac/tags/rel_27/bench/verilog
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	7962d 15h	/ethmac/tags/rel_27/bench/verilog

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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 267

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