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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 286

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Rev	Log message	Author	Age	Path
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7632d 12h	/ethmac/tags/rel_27/bench/verilog
281	Tests test_mac_full_duplex_receive 4-7 fixed to proper BD.	mohor	7765d 08h	/ethmac/tags/rel_27/bench/verilog
279	Underrun test fixed. Many other tests fixed.	mohor	7766d 10h	/ethmac/tags/rel_27/bench/verilog
274	Backup version. Not fully working.	tadejm	7774d 04h	/ethmac/tags/rel_27/bench/verilog
267	Full duplex control frames tested.	mohor	7830d 07h	/ethmac/tags/rel_27/bench/verilog
266	Flow control test almost finished.	mohor	7835d 06h	/ethmac/tags/rel_27/bench/verilog
263	test_mac_full_duplex_flow_control tests pretty much finished. TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) finished. TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps ) finished.	mohor	7835d 21h	/ethmac/tags/rel_27/bench/verilog
260	test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame finished.	mohor	7836d 10h	/ethmac/tags/rel_27/bench/verilog
254	Temp version.	mohor	7838d 03h	/ethmac/tags/rel_27/bench/verilog
252	Just some updates.	tadejm	7838d 06h	/ethmac/tags/rel_27/bench/verilog
243	Late collision is not reported any more.	tadejm	7843d 10h	/ethmac/tags/rel_27/bench/verilog
227	Changed BIST scan signals.	tadejm	7870d 06h	/ethmac/tags/rel_27/bench/verilog
223	Some code changed due to bug fixes.	tadejm	7870d 10h	/ethmac/tags/rel_27/bench/verilog
216	Bist signals added.	mohor	7877d 10h	/ethmac/tags/rel_27/bench/verilog
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	7879d 10h	/ethmac/tags/rel_27/bench/verilog
194	Full duplex tests modified and testbench bug repaired.	tadej	7898d 09h	/ethmac/tags/rel_27/bench/verilog
192	Some additional reports added	tadej	7900d 06h	/ethmac/tags/rel_27/bench/verilog
191	Bug repaired in eth_phy device	tadej	7900d 06h	/ethmac/tags/rel_27/bench/verilog
189	Simple testbench that includes eth_cop, eth_host and eth_memory modules. This testbench is used for testing the whole environment. Use tb_ethernet testbench for testing just the ethernet MAC core (many tests).	mohor	7900d 07h	/ethmac/tags/rel_27/bench/verilog
188	PHY changed.	tadej	7901d 03h	/ethmac/tags/rel_27/bench/verilog

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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 286

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