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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] - Rev 315

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Rev Log message Author Age Path
315 Updated testbench. Some more testcases, some repaired. tadejm 6091d 03h /ethmac/tags/rel_27/bench/verilog/
302 mbist signals updated according to newest convention markom 6140d 08h /ethmac/tags/rel_27/bench/verilog/
299 Artisan RAMs added. mohor 6198d 03h /ethmac/tags/rel_27/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 6266d 04h /ethmac/tags/rel_27/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 6399d 00h /ethmac/tags/rel_27/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 6400d 02h /ethmac/tags/rel_27/bench/verilog/
274 Backup version. Not fully working. tadejm 6407d 20h /ethmac/tags/rel_27/bench/verilog/
267 Full duplex control frames tested. mohor 6463d 23h /ethmac/tags/rel_27/bench/verilog/
266 Flow control test almost finished. mohor 6468d 22h /ethmac/tags/rel_27/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 6469d 13h /ethmac/tags/rel_27/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 6470d 02h /ethmac/tags/rel_27/bench/verilog/
254 Temp version. mohor 6471d 19h /ethmac/tags/rel_27/bench/verilog/
252 Just some updates. tadejm 6471d 22h /ethmac/tags/rel_27/bench/verilog/
243 Late collision is not reported any more. tadejm 6477d 02h /ethmac/tags/rel_27/bench/verilog/
227 Changed BIST scan signals. tadejm 6503d 23h /ethmac/tags/rel_27/bench/verilog/
223 Some code changed due to bug fixes. tadejm 6504d 02h /ethmac/tags/rel_27/bench/verilog/
216 Bist signals added. mohor 6511d 02h /ethmac/tags/rel_27/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6513d 02h /ethmac/tags/rel_27/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 6532d 01h /ethmac/tags/rel_27/bench/verilog/
192 Some additional reports added tadej 6533d 22h /ethmac/tags/rel_27/bench/verilog/

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