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[/] [ethmac/] [tags/] [rel_27/] [rtl/] - Rev 251

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Rev Log message Author Age Path
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7849d 09h /ethmac/tags/rel_27/rtl/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7849d 09h /ethmac/tags/rel_27/rtl/
248 wb_rst_i is used for MIIM reset. mohor 7850d 10h /ethmac/tags/rel_27/rtl/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7853d 13h /ethmac/tags/rel_27/rtl/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7854d 08h /ethmac/tags/rel_27/rtl/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7855d 05h /ethmac/tags/rel_27/rtl/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7855d 05h /ethmac/tags/rel_27/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7855d 05h /ethmac/tags/rel_27/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7855d 05h /ethmac/tags/rel_27/rtl/
238 Defines fixed to use generic RAM by default. mohor 7867d 09h /ethmac/tags/rel_27/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7869d 14h /ethmac/tags/rel_27/rtl/
232 fpga define added. mohor 7875d 08h /ethmac/tags/rel_27/rtl/
229 case changed to casex. mohor 7881d 06h /ethmac/tags/rel_27/rtl/
227 Changed BIST scan signals. tadejm 7881d 10h /ethmac/tags/rel_27/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7881d 11h /ethmac/tags/rel_27/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7885d 11h /ethmac/tags/rel_27/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7888d 11h /ethmac/tags/rel_27/rtl/
218 Typo error fixed. (When using Bist) mohor 7888d 13h /ethmac/tags/rel_27/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7889d 10h /ethmac/tags/rel_27/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7889d 10h /ethmac/tags/rel_27/rtl/
212 Minor $display change. mohor 7889d 10h /ethmac/tags/rel_27/rtl/
211 Bist added. mohor 7889d 11h /ethmac/tags/rel_27/rtl/
210 BIST added. mohor 7889d 11h /ethmac/tags/rel_27/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7906d 09h /ethmac/tags/rel_27/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7906d 09h /ethmac/tags/rel_27/rtl/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7909d 10h /ethmac/tags/rel_27/rtl/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7917d 12h /ethmac/tags/rel_27/rtl/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7918d 13h /ethmac/tags/rel_27/rtl/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7919d 13h /ethmac/tags/rel_27/rtl/
165 HASH improvement needed. mohor 7919d 16h /ethmac/tags/rel_27/rtl/

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