URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_27/] [rtl/] [verilog/] - Rev 324

Rev	Log message	Author	Age	Path
275	Fix MTxErr or prevent sending too big frames.	mohor	7780d 03h	/ethmac/tags/rel_27/rtl/verilog/
272	When control packets were received, they were ignored in some cases.	tadejm	7780d 22h	/ethmac/tags/rel_27/rtl/verilog/
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7782d 00h	/ethmac/tags/rel_27/rtl/verilog/
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7783d 00h	/ethmac/tags/rel_27/rtl/verilog/
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	7841d 23h	/ethmac/tags/rel_27/rtl/verilog/
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7842d 10h	/ethmac/tags/rel_27/rtl/verilog/
259	In loopback rx_clk is not looped back. Possible CRC error. Consider if usage of additional logic is necessery (FIFO for looping the data).	mohor	7843d 11h	/ethmac/tags/rel_27/rtl/verilog/
257	When TxUsedData and CtrlMux occur at the same time, byte counter needs to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.	mohor	7843d 12h	/ethmac/tags/rel_27/rtl/verilog/
256	TxDone and TxAbort changed so they're not propagated to the wishbone module when control frame is transmitted.	mohor	7843d 12h	/ethmac/tags/rel_27/rtl/verilog/
255	TPauseRq synchronized to tx_clk.	mohor	7843d 12h	/ethmac/tags/rel_27/rtl/verilog/