Rev |
Log message |
Author |
Age |
Path |
338 |
|
root |
5476d 10h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
335 |
New directory structure. |
root |
5533d 15h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
324 |
This commit was manufactured by cvs2svn to create tag 'rel_27'. |
|
7307d 15h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
323 |
Accidently deleted line put back. |
igorm |
7307d 15h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
321 |
- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries |
igorm |
7311d 10h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
304 |
WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
tadejm |
7477d 07h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
302 |
mbist signals updated according to newest convention |
markom |
7503d 17h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
280 |
Reset has priority in some flipflops. |
mohor |
7763d 10h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
278 |
A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked. |
mohor |
7763d 12h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
272 |
When control packets were received, they were ignored in some cases. |
tadejm |
7771d 11h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
270 |
When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set. |
mohor |
7772d 13h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
269 |
When in full duplex, transmit was sometimes blocked. Fixed. |
mohor |
7773d 13h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
264 |
Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed. |
mohor |
7832d 12h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
261 |
Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized. |
mohor |
7832d 23h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
250 |
AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode. |
mohor |
7835d 08h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
239 |
RxError is not generated when small frame reception is enabled and small
frames are received. |
tadejm |
7841d 03h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
229 |
case changed to casex. |
mohor |
7867d 04h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
227 |
Changed BIST scan signals. |
tadejm |
7867d 08h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
226 |
Igor added WB burst support and repaired BUG when handling TX under-run and retry. |
tadejm |
7867d 10h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
221 |
TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed. |
mohor |
7871d 09h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
219 |
txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished. |
mohor |
7874d 10h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
210 |
BIST added. |
mohor |
7875d 09h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
167 |
Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. |
mohor |
7904d 11h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
166 |
Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated. |
mohor |
7905d 11h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
164 |
Ethernet debug registers removed. |
mohor |
7905d 15h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
159 |
Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized. |
mohor |
7907d 09h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
150 |
Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK. |
mohor |
7911d 06h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
134 |
Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more. |
mohor |
7932d 06h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
127 |
WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed. |
mohor |
7952d 07h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |
119 |
Ram , used for BDs changed from generic_spram to eth_spram_256x32. |
mohor |
7954d 10h |
/ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v |