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[/] [ethmac/] [tags/] [rel_27/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 338

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219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7874d 04h /ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v
210 BIST added. mohor 7875d 03h /ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7904d 06h /ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7905d 06h /ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 7905d 09h /ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7907d 03h /ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7911d 01h /ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7932d 00h /ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7952d 01h /ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7954d 04h /ethmac/tags/rel_27/rtl/verilog/eth_wishbone.v

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